Physical Design Team Lead

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is a hyper-growth connectivity company building the purpose-built silicon that powers rack-scale AI infrastructure. As a Principal Physical Design Engineer and Team Lead in Israel, you will lead physical design teams that take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout. You will set the technical direction, drive execution across multiple projects, and grow the engineers around you, partnering closely with RTL, DFT, analog, and architecture teams. Your work will directly shape the performance, power, and area of products that connect the world's most demanding AI platforms. Key Responsibilities Technical Leadership and Team Execution Lead and mentor physical design engineers, setting priorities, assigning work, and ensuring high-quality, on-time delivery Drive physical design projects end to end, including planning, scheduling, risk management, and status reporting Define and evolve physical design methodologies, flows, and best practices across the team Physical Implementation Own block-level and top-level implementation: floorplanning, placement, clock tree synthesis, routing, and optimization Drive timing closure, power integrity, and signal integrity to meet aggressive PPA targets in advanced process nodes Lead physical verification and sign-off activities, including STA, IR/EM, DRC, LVS, and ECO management Cross-Functional Collaboration Partner with RTL design, DFT, analog, and architecture teams to resolve cross-domain implementation challenges early Work with foundry, EDA vendors, and IP providers to ensure smooth tapeout and silicon bring-up Contribute to hiring, onboarding, and professional development of team members Basic Qualifications 10+ years of hands-on experience in physical design of complex SoCs or ASICs Proven experience leading projects and technical teams through one or more full-chip tapeouts Deep expertise with industry-standard physical design and sign-off tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre) Strong knowledge of timing closure, power/clock distribution, and physical verification in advanced process nodes Excellent communication skills and the ability to work in a fully in-person, collaborative environment Preferred Qualifications Experience with high-speed interface designs such as PCIe, Ethernet, or SerDes-based products Proficiency in scripting languages such as Tcl, Python, or Perl for flow automation Experience with hierarchical design, low-power methodologies, and ECO-driven closure Demonstrated ability to mentor engineers and drive continuous improvement in team processes We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.